Datasheet

TPL0501
SLIS136A –SEPTEMBER 2011– REVISED SEPTEMBER 2011 www.ti.com
ANALOG SPECIFICATIONS (continued)
Typical Values are specified at VDD=5V and operating temperature of 25 C
PARAMETER CONDITIONS MIN TYP MAX UNIT
T
CV
Ratiometric temperature coefficient Wiper set at mid-scale 4 ppm/°C
BW Bandwidth Wiper set at mid-scale, TPL0501-100, C
LOAD
=10pF 265 kHz
T
SW
Wiper settling time TPL0501-100 3 µS
V
H
= 1V
RMS
at 1kHz,
THD Total harmonic distortion 0.005 %
V
L
= V
DD
/2, measurement at W
RHEOSTAT MODE (Measurements between Wi and Li with Hi not connected, or between Wi and Hi with Li not connected)
RINL Integral non-linearity –1 1 LSB
RDNL Differential non-linearity –0.5 0.5 LSB
R
OFFSET
Offset 0 0.5 2 LSB
Code=0x00h, L Floating, Input applied to W, 10 pF
RBW Bandwidth 60 kHz
on H
OPERATING SPECIFICATIONS
Typical Values are specified at VDD=5V and operating temperature of 25 C
PARAMETER CONDITIONS MIN TYP MAX UNIT
I
DD(STBY)
V
DD
Standby current 0.3 8 µA
I
IN-DIG
Digital pins leakage current (SCLK, DIN, CS inputs) –1 1 µA
Digital Input= 1.8V, VDD=2.7V 5 µA
I
DD(SUPPL
V
DD
Supply Current
Y)
Digital Input= 1.8V, VDD=5V 500 µA
SERIAL INTERFACE SPECS (SCLK, DIN, CS Inputs)
V
IH
Input high voltage V
DD
= 2.7 V to 5.5 V 1.8 5.5 V
V
IL
Input low voltage SCLK, DIN, CS Inputs 0 0.6 V
C
IN
Pin capacitance SCLK, DIN, CS Inputs 7 10 pF
SPI INTERFACE TIMING CHARACTERISTICS
f
SCLK
SCLK Frequency 25 MHz
t
SCP
SCLK Period 40 ns
t
SCH
SCLK High time 20 ns
t
SCL
SCLK Low time 20 ns
t
DS
DIN to SCLK setup time 5 ns
t
DH
DIN hold after SCLK 5 ns
t
CSS
CS Fall to SCLK rise setup time 15 ns
t
CSW
CS Pulse width high 40 ns
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