Datasheet

Start
Address (01_1110)
0 Ack
Command (00000000)
Ack
Start
Address (01_1110)
0 Ack
Command (00000000)
Ack
reStart
Address (01_1110)
1 Ack Data Byte
I
2
C Write to A Register
I
2
C Read From A Register
Data Stop
noAck
Stop
Ack
From Processor to DPOT
From toDPOT Processor
SDA
SCL
Start Condition Stop Condition
S
P
TPL0401A
TPL0401B
TPL0401C
www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012
SLAVE ADDRESS
TPL0401A, TPL0401C
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
0 1 0 1 1 1 0 R/W
TPL0401B
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
0 1 1 1 1 1 0 R/W
WRITE AND READ PROTOCOL
Standard I
2
C Interface Details
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by the master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 13). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output
during the high of the ACK-related clock pulse.
Figure 12. Definition of Start and Stop Conditions
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