Datasheet

SDA

SCL

Data Line

Stable

Data Valid

Change

of Data

Allowed

Data Output

by Transmitter

Data Output

by Receiver

SCL from

Master

NACK

Start

Condition

ACK

Clock Pulse for

Acknowledgment

TPL0401A

TPL0401B

TPL0401C

SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012

www.ti.com

The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The

data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and

acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle

for the ACK.

On the I

C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 13).

Figure 13. Bit Transfer

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 13).

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that

acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during

the high pulse of the ACK-related clock period (see Figure 14). Setup and hold times must be taken into account.

Figure 14. Acknowledgement on the I

C Bus

Product Folder Link(s): TPL0401A TPL0401B TPL0401C