Datasheet

TPL0202
SLIS135C –DECEMBER 2010–REVISED JUNE 2012 www.ti.com
SPI INTERFACE TIMING REQUIREMENTS
V
DD
= 2.7V to 5.5V, V
H
= V
DD
, V
L
= GND, T
A
= -40°C to 85°C (unless otherwise noted)
MIN TYP UNITMAX
f
SCLK
SLCK frequency 5 MHz
t
SCP
SCLK period 200 ns
t
SCH
SCLK high time 80 ns
t
SCL
SCLK low time 80 ns
t
CSS
CS fall to SCLK rise setup time 80 ns
t
CSH
SCLK rise to CS hold time 0 ns
t
DS
DIN to SCLK setup time 50 ns
t
DH
DIN hold after SCLK rise to CS fall 0 ns
t
CS0
SCLK rise to CS fall 20 ns
t
CS1
CS rise to SCLK rise hold 80 ns
t
CSW
CS pulse width high 200 ns
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