Datasheet

VDD
R1
DNI
R2
DNI
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ALT_VDD
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
J14
2
3
4
5
6
1
2
3
4
5
6
7
HEADERl7
14
13
12
11
10
9
8
HA
LA
WA
HB
LB
WB
A2
TPL0102PW
HA
LA
HB
LB
A2
WA
WB
VDD
A0
A1
GND
SCL
SDA
VSS
VDD
A0
A1
SCL
SDA
VSS
C2
0.1 Fμ
C1
0.1 Fμ
VSS
VSS
GND
VSS
ALT_VDD
VDD
GND
VDD
1
2
3
J4
1
2
J5
2
3
4
5
6
1
2
3
4
5
6
7
14
13
12
11
10
9
8
HA
LA
WA
HB
LB
WB
A2
TPL0102RUC
HA
LA
HB
LB
A2
WA
WB
VDD
A0
A1
GND
SCL
SDA
VSS
VDD
A0
A1
SCL
SDA
VSS
C7
0.1 Fμ
C6
0.1 Fμ
VDD
A0
GND
VDD
A1
GND
VDD
A2
GND
A2
1
2
3
VDD
A2
1
2
3
VDD
A1
1
2
3
VDD
A0
J3
J2
J1
A1A0
Alternate QFN Footprint
HA
HA
GND
LA
1
2
J8
J10
LA
GND
J11
J13
J12
WA
HB
WA
LA
WA
HB
GND
HB
LB
LB
GND
LB
WB
GND
WB
WB
1
2
1
2
1
2
1
2
1
2
HA
J9
GND
U1
TPL0102 Evaluation Module
U2
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Setup Procedure
1. Insert header caps in J1, J2, J3 to set A2, A1, A0 respectively. The board is shipped with the following
settings: A2=0, A1=0, A0=1.
2. Connect the I
2
C bus of the host processor to the board via connector J14 (pins marked SCL, SDA).
Also connect the GND pin on J14 to GND of the host processor.
3. Apply the positive supply voltage (VDD) to center pin of J4. Apply GND to lowest pin of J4.
4. Apply the negative supply voltage (VSS) to J5. The board is shipped with a header cap that connects
VSS to GND.
5. Write to the TPL0102 data registers per protocol in the datasheet (Lit# SLIS134).
6. Measure resistance between H, W, L terminals as appropriate on headers J8-J13.
TPL0102 EVM Schematic
2
TPL0102 Evaluation Module SLIU004–March 2011
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