Datasheet

TPL0102

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SLIS134B –MARCH 2011–REVISED AUGUST 2011

Standard I

C Interface Details

The bidirectional I

C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

C communication with this device is initiated by the master sending a start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 6). After the start condition, the device address byte

is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call

address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output

during the high of the ACK-related clock pulse

Figure 6. Definition of Start and Stop Conditions

The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The

data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and

acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle

for the ACK. On the I

C bus, only one data bit is transferred during each clock pulse. The data on the SDA line

must remain stable during the high pulse of the clock period, as changes in the data line at this time are

interpreted as control commands (start or stop) (see Figure 7).

Figure 7. Bit Transfer

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 6).

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that

acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during

the high pulse of the ACK-related clock period (see Figure 8). Setup and hold times must be taken into account.