Datasheet
SLIS110A − APRIL 2003 − REVISED MAY 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dc electrical characteristics, V
DD
= 5 V ±5%, input frequency before prescaler = 4 MHz to 20 MHz
(±0.5%), T
A
= −40°C to 125°C (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
I
DD(Q)
Quiescent current V
DD
= 5 V 7.5 mA
I
DD(OP)
Operating current V
DD
= 5 V, XIN = 8 MHz 20 mA
V
mid0
Midpoint voltage V
DD
= 5 V, I
Source
= 2 mA 2.3 2.5 2.55 V
V
mid1
Midpoint voltage V
DD
= 5 V, I
Sink
= 2 mA 2.4 2.5 2.7 V
V
mid2
Midpoint voltage V
DD
= 5 V, I
L
= 0 mA 2.4 2.5 2.6 V
Rpull0 Internal pullup resistor CS, SDI, SCLK, TEST V
IN
= GND 30 kΩ
Rpull1 Internal pulldown resistor INT/HOLD V
IN
= V
DD
20 kΩ
I
lkg
Input leakage current CS, SDI, SCLK,
INT/HOLD, TEST
Measured at GND and V
DD
,
V
DD
= 5.5 V = V
IN
±3 µA
V
IL
Low-level input voltage INT/HOLD, CS,
TEST
, SDI, SCLK
30% of
V
DD
V
IH
High-level input voltage INT/HOLD, CS,
TEST
, SDI, SCLK
70% of
V
DD
V
OL
Low-level output voltage SDO I
Sink
= 4 mA, V
DD
= 5 V 0.7 V
V
OH
High-level output voltage SDO I
Source
= 100 µA, V
DD
= 5 V 4.4 V
I
lkg(OL)
Low-level leakage current SDO
Measured at GND and V
DD
= 5 V,
SDO in high impedance
−10 10 µA
V
OL(XOUT)
Low-level output voltage I
Sink
= 500 µA, V
DD
= 4.5 V 1.5 V
V
OH(XOUT)
High-level output voltage I
Source
= 500 µA, V
DD
= 5 V 4.4 V
V
hyst
Hysteresis voltage INT/HOLD, CS, XIN, SDI,
SCLK, TEST
0.4 V
Input Amplifiers
V
OH(1)
CH1FB and CH2FB high-level output voltage
V
DD
= 5 V, I
Source
= 100 µA
V
DD
–
0.05
V
DD
–
0.02
V
V
OH(1)
CH1FB and CH2FB high-level output voltage
V
DD
= 5 V, I
Source
= 2 mA
V
DD
–
0.5
V
V
OL(1)
CH1FB and CH2FB low-level output voltage
I
Sink
= 100 µA 15 50
mV
V
OL(1)
CH1FB and CH2FB low-level output voltage
I
Sink
= 2 mA
500
mV
C
ATTEN
Cross-coupling attenuation CH1FB and
CH2FB
f
in
max
(ch1)
= 20 kHz, measured on
channel 2
40 dB
Av Open-loop gain 60 100 dB
G
BW
Gain bandwidth product Input range 0.5 V to 4.5 V 1 2.6 MHz
V
IN
Input voltage range 0.05
V
DD
–
0.05
V
V
(offset)
Offset voltage at input −10 10 mV
CMRR Common-mode rejection ratio Inputs at V
mid
f
in
= 0 to 20 kHz 60 80 dB
PM Phase margin Gain = 1, C
L
= 200 pF, R
L
= 100 kΩ 45 deg
Prescaler, XIN
V
OSC
Minimum input peak amplitude
(1)
V
DD
= V
min,
oscillator inverter biased
feedback resistor 1 MΩ, f
osc
= 24 MHz
150 mV
C
IN
Input capacitance Assured by design 7 pF
I
lkg(XIN)
Leakage current −1 1 µA
NOTE 1: 150-mV input amplitude on the 4-MHz clock input only applies if the feedback network is completed. Without the feedback network, the
4-MHz signal should be at 0−5V levels.