Datasheet

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  
SLIS110A − APRIL 2003 − REVISED MAY 2005
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Programmable
Gain
V
ref
+
−
Mux
3
rd
Order AAF
SAR
10-Bit ADC
fs = 200 kHz
<1:10>
Programmable
Band-Pass
Filter
Rectifier
Programmable
Integrator
R2R
10-Bit DAC
fs = 200 kHz
V
DD
/2
SPI
Test Mode
DSP Control
DSP
CH1P
CH1N
CH1FB
CH2P
CH2N
CH2FB
+
−
+
−
+
−
V
DD
GND OUT SDO SDI SCLK TESTCS INT/HOLD XIN XOUT