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Input Undervoltage Alarm Terminal (A
OUT
)
Reset Delay Timer Terminal (REST)
Reset Terminal (RESET)
Main Regulator Output Terminal (V
OUT
)
Low-Power-Mode Terminal (CLP)
Switch-Output Terminal (5Vg)
5Vg-Enable Terminal (5Vg_ENABLE)
TPIC74100-Q1
BUCK/BOOST SWITCH-MODE REGULATOR
SLIS125 – DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
The A
OUT
terminal is an open-drain output that asserts low when the input voltage falls below the set threshold
on the A
IN
input.
The REST terminal sets the desired delay time to assert the RESET terminal low after the 5-V supply has
exceeded 4.65 V (typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in
the range of 2.2 nF to 150 nF. The delay time is calculated using the following equation:
RESET delay = C
(REST)
× 1 ms, where C
(REST)
has nF units
The RESET terminal is an open-drain output. The power-on reset output is asserted low until the output voltage
exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE
terminal is low, RESET is immediately asserted low regardless of the output voltage.
The V
OUT
terminal is the output of the switch-mode regulated supply. This terminal requires a filter capacitor with
low-ESR characteristics to minimize output ripple voltage. For stability, a capacitor with 22 µ F to 470 µ F should
be used. The total capacitance at pin V
OUT
and pin 5Vg must be less than or equal to 470 µ F.
The CLP terminal controls the low-power mode of the device. An external low digital signal switches the device
to low-power mode or normal mode when the input is high.
The 5Vg terminal switches the 5-V regulated output. The output voltage of the regulator can be enabled or
disabled using this low-r
DS(on)
internal switch. This switch has a current-limiting function to prevent generation of
a reset signal at turnon caused by the capacitive load on the output or overload condition. When the switch is
enabled, the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor is
fully charged. This deviation depends on the characteristics of the capacitors on V
OUT
and 5Vg.
The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg.
For the functional terminal, 5Vg_ENABLE results in the following table:
5Vg_ENABLE Function
0 5Vg is off
Open (internal pulldown = 500 k Ω ) 5Vg is off
1 5Vg is on
8
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