Datasheet

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    
SLIS056A − FEBRUARY 1995 − REVISED MARCH 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
switching characteristics, V
CC
= 5 V, T
C
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w
Clock cycle period pulse duration, SCLK See Figure 1 250 555 ns
t
wH(SCLK)
Pulse duration, SCLK high See Figure 1 100 248 ns
t
wL(SCLK)
Pulse duration, SCLK low See Figure 1 100 248 ns
t
pd1
Propagation delay from falling edge of CS to SDO valid
CS = 0.8 V to SDO low
impedance (see Figure 1)
150 300 ns
t
pd2
Propagation delay from rising edge of CS to SDO 3-state CS = 2 V to SDO 3-state 150 200 ns
t
pd3
Propagation delay from SCLK to SDO valid CS < 0.8 V 80 172 ns
t
r(SDO)
Rise time of SDO C
load
= 200 pF 30 50 ns
t
f(SDO)
Fall time of SDO C
load
= 200 pF 30 50 ns
t
(stb)
Short-to-battery/shorted-load/open-load deglitch time See Figures 5 and 6 25 70 100 µs
t
d(on)
Turn-on delay time, rising edge of CS to drain 0.4 5 10
t
d(off)
Turn-off delay time, rising edge of CS to drain
V
bat
= 14 V,
R = 30
0.4 5 15
s
t
r(drain)
Rise time of drain terminal
V
bat
= 14 V,
R
load
= 30 Ω
0.4 5 10
µs
t
f(drain)
Fall time of drain terminal
load
0.4 5 10
f
(SCLK)
Serial clock frequency 1.8 4 MHz
t
cyc(ref)
Short-to-battery sense cycle time See Figure 5 1.6 4 6.4 ms
t
w(sense)
Short-to-battery sense pulse duration See Figure 5 25 70 100 µs
t
su1
Setup to/from the fall edge of CS to the rising edge of SCLK See Figure 1 150 200 ns
t
su(SDI)
Setup time, SDI to SCLK See Figure 1 25 55 ns
t
h(SDI)
Hold time, SDI after SCLK See Figure 1 10 55 ns
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
R
θJA
Junction-to-ambient thermal resistance All outputs with equal power 50 °C
R
θJC
Junction-to-case thermal resistance All outputs with equal power 10 °C