Datasheet

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APPLICATION INFORMATION
IO3
GND
IO2
IO1
V
BUS
D+
D–
GND
0.1 µF
V
CC
USB
Controller
R
T
R
T
Detailed Description
TPD3E001
LOW-CAPACITANCE 3-CHANNEL ± 15-kV ESD-PROTECTION ARRAY
FOR HIGH-SPEED DATA INTERFACES
SLLS683D – JULY 2006 – REVISED APRIL 2007
When placed near the connector, the TPD3E001 ESD solution offers little or no signal distortion during normal
operation due to low IO capacitance and ultra-low leakage current specifications. The TPD3E001 ensures that
the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper
operation, the following layout/ design guidelines should be followed:
1. Place the TPD3E001 solution close to the connector. This allows the TPD3E001 to take away the energy
associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place a 0.1- µ F capacitor very close to the V
CC
pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.
3. Ensure that there is enough metallization for the V
CC
and GND loop. During normal operation, the
TPD3E001 consumes nA leakage current. But during the ESD event, V
CC
and GND may see 15 A to
30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the
energy associated with the ESD strike.
4. Leave the unused IO pins floating.
5. The V
CC
pin can be connected in two different ways:
a. If the V
CC
pin is connected to the system power supply, the TPD3E001 works as a transient suppressor
for any signal swing above V
CC
+ V
F
. A 0.1- µ F capacitor on the device V
CC
pin is recommended for ESD
bypass.
b. If the V
CC
pin is not connected to the system power supply, the TPD3E001 can tolerate higher signal
swing in the range up to 10 V. Please note that a 0.1- µ F capacitor is still recommended at the V
CC
pin for
ESD bypass.
5
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