Datasheet

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IO3
GND
IO2IO1
V
CC
TPD3E001
LOW-CAPACITANCE 3-CHANNEL ± 15-kV ESD-PROTECTION ARRAY
FOR HIGH-SPEED DATA INTERFACES
SLLS683D – JULY 2006 – REVISED APRIL 2007
LOGIC BLOCK DIAGRAM
PIN DESCRIPTION
DRL DRY DRS
NAME FUNCTION
NO. NO. NO.
1, 2, 4 1, 2, 4 1, 2, 4 IOx ESD-protected channel
3 3 3 GND Ground
Power-supply input. Bypass V
CC
to GND with a 0.1- µ F ceramic
5 6 6 V
CC
capacitor.
5 5 N.C. No connection. Not internally connected.
EP EP Exposed pad. Connect to GND.
2
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