Datasheet

0
1
2
3
4
5
6
Voltage - V
15 17.5 20 22.5 25 27.5
t - Time - sm
B Port
A Port
TPD12S016
SLLSE96D –SEPTEMBER 2011–REVISED DECEMBER 2012 www.ti.com
Figure 4. DDC Level Shifter Operation (B to A Direction)
Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of
the bus is releasing the signal.
Noise Considerations:
Ground offset between the TPD12S016 ground and the ground of devices on port A of the TPD12S016 must be
avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of
current at 0.4 V will have an output resistance of 133 Ω or less (R = E / I). Such a driver will share enough
current with the port A output pull-down of the TPD12S016 to be seen as a LOW as long as the ground offset is
zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since V
ILC
can be as low as
90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not
exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the port A of the TPD12S016
as their output LOW levels will not be recognized by the TPD12S016 as a LOW. If the TPD12S016 is placed in
an application where the VIL of port A of the TPD12S016 does not go below its V
ILC
it will pull port B LOW
initially when port A input transitions LOW but the port B will return HIGH, so it will not reproduce the port A input
on port B. Such applications should be avoided. Port B is interoperable with all I2C-bus slaves, masters and
repeaters.
Resistor Pull-Up Value Selection
The system is designed to work properly with no external pull-up resistors on the DDC, CEC, and HPD lines.
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