Datasheet

300 mV
150 mV
Port A
Port B
VCCA
5 VOUT
700
mV
ACCEL
I
ACCEL
R
PUA
GLITCH
FILTER
CMP1
CMP2
l
R
PUB
DDC
Lines
Only
TPD12S016
www.ti.com SLLSE96D –SEPTEMBER 2011–REVISED DECEMBER 2012
APPLICATION INFORMATION
DDC/CEC LEVEL SHIFT Circuit Operation
The TPD12S016 enables DDC translation from VCCA (system side) voltage levels to 5V (HDMI cable side)
voltage levels without degradation of system performance. The TPD12S016 contains 2 bidirectional open-drain
buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side
DDC-bus and the 5V DDC-bus. The port B I/Os are over-voltage tolerant to 5.5 V even when the device is un-
powered. After power-up and with the LS_OE and CT_HPD pins HIGH, a LOW level on port A (below
approximately V
ILC
= 0.08×VCCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port
B down to V
OLB
V. When port A rises above approximately 0.10×VCCA V, the port B pull-down driver is turned
off and the internal pull-up resistor pulls the pin HIGH. When port B falls first and goes below 0.3×5VOUT, a
CMOS hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to
approximately VOLA=0.16×VCCA V. The port B pull-down is not enabled unless the port A voltage goes below
V
ILC
. If the port A low voltage goes below V
ILC
, the port B pull-down driver is enabled until port A rises above
(V
ILC
+ ΔV
T-HYSTA
), then port B, if not externally driven LOW, will continue to rise being pulled up by the internal
pull-up resistor.
Figure 3. DDC/CEC Level Shifter Block Diagram
DDC/CEC Level Shifter Operational Notes for VCCA=1.8V
• The threshold of CMP1 is ~150mV ± the 40mV of total hysteresis.
• The comparator will trip for a falling waveform at ~130mV
• The comparator will trip for a rising waveform at ~170mV
• To be recognized as a zero, the level at Port A must first go below 130mV (V
ILC
in spec) and then stay below
170mV (V
ILA
in spec)
• To be recognized as a one, the level at A must first go above 170mV and then stay above 130mV
• V
ILC
is set to 110mV in Electrical Characteristics Table to give some margin to the 130mV
• V
ILA
is set to 140mV in the Electrical Characteristics Table to give some margin to the 170mV
• V
IHA
is set to 70% of VCCA to be consistent with standard CMOS levels
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links :TPD12S016