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TPD12S015

www.ti.com

SLLSE19E –DECEMBER 2009–REVISED JUNE 2013

HDMI COMPANION CHIP WITH STEP-UP DC-DC, I

C LEVEL SHIFTER, AND HIGH-SPEED

ESD CLAMPS FOR PORTABLE APPLICATIONS

Check for Samples: TPD12S015

FEATURES

• HDMI 1.3 Data Rate • IEC 61000-4-2 (Level 4) System Level ESD

Compliance

• HDMI High-Speed Differential Signals -3 dB

Bandwidth Exceeds 6.4 Gbps • Integrated I

OFF

and Backdrive Current

Protection

• Excellent Matching Capacitance (0.05 pF) in

Each Differential Signal Pair • Space-saving 1.6 mm × 2.8 mm WCSP (YFF)

Package

• Internal Boost Converter to Generate 5 V from

a 2.3- to 5.5-V Battery Voltage

APPLICATIONS

• HDMI Minimum Current Limit and Short-circuit

• Smart Phones

Protection at 5VOUT Pin

• Multimedia Phones

• Flexible Power Saving Modes Through

Seperate Control Pins

• Digital Camcorders

• Auto Direction Sensing Level Shifting in the

• Digital Still Cameras

CEC, SDA, SCL Lines Drive up to 750pF Load

• Portable Game Consoles

• Seamless Type C and Type D Connector

Routing with Flow-Through Pin Mapping

YFF PACKAGE PIN MAPPING

YFF PACKAGE

1 2 3 4

(TOP VIEW)

A LS_OE V

CCA

D2+ D2–

B SCL_A CEC_A GND D1+

C SDA_A HPD_A GND D1–

D CT_CP_HPD GND CEC_B D0+

E FB GND SCL_B D0–

F 5VOUT SW SDA_B CLK+

G P

GND

BAT

HPD_B CLK–

For package dimensions, see the

Mechanical Drawing at the end of this

document.

DESCRIPTION

The TPD12S015 is an integrated HDMI ESD solution. The device pin mapping matches the HDMI Type C and

Type D connector with four differential pairs. This device offers eight low-capacitance ESD clamps, allowing

HDMI 1.3 data rates. The integrated ESD clamps and resistors provide good matching between each differential

signal pair, which allows an advantage over discrete ESD clamp solutions where variations between ESD clamps

degrade the differential signal quality.

The TPD12S015 provides a regulated 5 V output (5VOUT) for sourcing the HDMI power line. The regulated 5 V

output supplies up to 55 mA to the HDMI receiver. The control of 5VOUT and the hot plug detect (HPD) circuitry

is independent of the LS_OE control signal and is controlled by the CT_CP_HPD pin. This independent control

enables the detection scheme (5VOUT + HPD) to be active before enabling the HDMI link.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 HDMI COMPANION CHIP WITH STEP-UP DC-DC, I2C LEVEL SHIFTER, AND HIGH-SPEED ESD CLAMPS FOR PORTABLE APPLICATIONS Check for Samples: TPD12S015 FEATURES 1 • • • • • • • • HDMI 1.3 Data Rate HDMI High-Speed Differential Signals -3 dB Bandwidth Exceeds 6.4 Gbps Excellent Matching Capacitance (0.05 pF) in Each Differential Signal Pair Internal Boost Converter to Generate 5 V from a 2.3- to 5.
PAGE 2
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com There are three non-inverting bi-directional translation circuits for the SDA, SCL, and CEC lines. Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6V . On the B side, the SCL_B and SDA_B each have an internal 1.75 kΩ pullup connected to the regulated 5 V rail (5VOUT). The SCL and SDA pins meet the I2C specification and drive up to 750 pF loads. The CEC_B pin has an internal 27 kΩ pullup to an internal 3.3 V supply.
PAGE 3
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 CIRCUIT BLOCK DIAGRAM VBAT FB (IEC) SW CT_CP_HPD 5VOUT (IEC) 5V DC/DC 470k PGND D0+, D0D1+, D1D2+, D2CLK+, CLK8 (IEC) HDMI ESD Clamp (x8) LS_OE_INTERNAL 5VOUT VCCA 3.3V (Internal ) LDO 470k HPD_B (IEC) 11k LS_OE VCCA HPD_A CT_CP_HPD VCCA 3.3V (Internal) 10k 26k±15% CEC_B (IEC) CEC_A 5VOUT VCCA 1.75k 10k ERC SCL_B (IEC) SCL_A 5VOUT VCCA 1.
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TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com TERMINAL FUNCTIONS TERMINAL 4 TYPE DESCRIPTION F1 Pwr O DC/DC output. The 5-V power pin can supply 55 mA regulated current to the HDMI receiver. Separate DC/DC converter control pin CT_CP_HPD disables the DC/DC converter when operating at low-power mode. CEC_A B2 I/O System-side CEC bus I/O. This pin is bi-directional and referenced to VCCA. CEC_B D3 I/O HDMI-side CEC bus I/O.
PAGE 5
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VCCA Supply voltage range VBAT Supply voltage range VI Input voltage range Voltage range applied to any output in the highimpedance or power-off state (2) VO MAX UNIT 4.0 V –0.3 6.5 SCL_A, SDA_A, CEC_A , CT_CP_HPD, LS_OE –0.3 4.0 SCL_B, SDA_B, CEC_B, D, CLK –0.3 6.0 SCL_A, SDA_A, CEC_A, HPD_A –0.3 4.
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TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com ESD RATINGS TYP UNIT Human Body Model JESD22 A114-B PARAMETER ALL PINS 2.
PAGE 7
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 DC-DC Converter (continued) PARAMETER TEST CONDITIONS TYP MAX UNIT 30 50 µA VBAT = 2.3 V to 5.5 V, IO = 0 mA, CT_CP_HPD Low 2 µA IDD(system off) Power supply current from VBAT, VCCA =0V VCCA = 0 V 5 µA I_inrush (startup) Inrush current, average over T_startup time VBAT = 2.3 V to 5.
PAGE 8
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com Voltage Level Shifter: CEC Lines (x_A/x_B Ports) TA = –40°C to 85°C unless otherwise specified PARAMETER TEST CONDITIONS VCCA MIN VCCA × 0.8 VOHA IOH = –10 μA, VI = VIH 1.1 V to 3.6 V VOLA IOL = 10 µA, VI = VIL 1.1 V to 3.6 V VOHB IOH = –10 μA, VI = VIH IOL = 3 mA, VI = VIL VOLB TYP V 0.4 1.1 V to 3.6 V 40 CEC_B (VT+ – VT–) 1.1 V to 3.
PAGE 9
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 SWITCHING CHARACTERISTICS PARAMETER CL TEST CONDITIONS MIN TYP MAX UNIT Bus load capacitance (B side) 750 pF Bus load capacitance (A side) 15 Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2V VCCA = 1.
PAGE 10
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5V (continued) VCCA = 1.
PAGE 11
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8V VCCA = 1.8 V tPLH PARAMETER PINS TEST CONDITIONS Propagation delay A to B CEC Channels Enabled MIN tf tr 13 B to A 0.
PAGE 12
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5V VCCA = 2.5 V tPLH PARAMETER PINS TEST CONDITIONS Propagation delay B to A CEC Channels Enabled tPLH MIN TYP MAX 10 B to A UNIT μs 9 tf A port fall time A Port CEC Channels Enabled 0.37 ns tr A port rise time A Port CEC Channels Enabled 0.39 ns Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3V VCCA = 3.
PAGE 13
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 APPLICATION INFORMATION DDC/CEC Level Shift Circuit Operation The TPD12S015 enables DDC translation from VCCA (system side) voltage levels to 5V (HDMI cable side) voltage levels without degradation of system performance. The TPD12S015 contains two bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side DDC-bus and the 5V DDC-bus.
PAGE 14
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com Figure 2. DDC/CEC Level Shifter Operation (B to A Direction) Rise-Time Accelerators The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of the bus is releasing the signal.
PAGE 15
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 Power-Save Mode The TPD12S015 integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage.
PAGE 16
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com Parameter f is the switching frequency and ΔIL is the ripple current in the inductor, i.e., 20% x IL. With this calculated value and the calculated currents, it is possible to choose a suitable inductor. In typical applications a 1.0 μH inductance is recommended. The device has been optimized to operate with inductance values between 1.0 μH and 1.3 μH. It is recommended that an inductance value of at least 1.
PAGE 17
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 Table 1. Passive Components: Recommended Minimum Effective Values COMPONENT MIN TARGET MAX UNIT CIN 1.2 4.7 6.5 μF COUT 1.2 4.7 10 μF LIN 0.7 1 1.3 μH VCCA 402 Cvcca GND Layer 1 Layer 2 5VOUT 603 Cout SW PGND 402 Cin 805 Lin VBAT Figure 3. Board Layout (DC-DC Components) (Top View) List of components: • LIN = MURATA LQM21PN1R0MC0 or LIN = Toko MDT2010-CN1R0 • CIN = MURATA GRM188R60J225ME19 (2.2 μF, 6.
PAGE 18
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com probe. Top Segment Middle Segment Bottom Segment Figure 4. TPD12S015 EVM Top and Bottom View The EVM board has 6 layers.
PAGE 19
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 Figure 5. Layer 1: High-Speed Signal layer Figure 6.
PAGE 20
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS 75 5.5 65 ICCB Current (mA) 5.4 ICC_5VOUT 5VOUT 5.3 60 5.2 55 5.1 50 5.0 45 4.9 40 4.8 35 4.7 30 4.6 25 4.5 20 4.4 15 4.3 10 4.2 5 4.1 0 5VOUT Voltage (V) 70 4.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Time (us) Figure 7. Load Transient Response 5.040 VBAT 5VOUT (20mA) 5VOUT (60mA) 4.1 VBAT Voltage (V) 4.0 5.020 5.000 3.9 4.980 3.8 4.960 3.7 4.940 3.6 4.
PAGE 21
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) 6.0 VCCA = VIH = 2.5 V, VBAT = 3.6 V 5.5 5.0 4.5 4.0 Voltage (V) 3.5 3.0 2.5 2.0 CT_CP_HPD 5VOUT (55 mA) 5VOUT(65 mA) 1.5 1.0 0.5 0.0 -0.5 -1.0 -50 0 50 100 150 200 250 300 Time (us) Figure 9. tSTART 6 VCCA = VIH = 2.5 V, VBAT = 3.6 V 5 CT_CP_HPD 5VOUT (55mA) 5VOUT (65mA) Voltage (V) 4 3 2 1 0 -1 0 500 1000 1500 2000 2500 3000 3500 4000 Time (us) Figure 10.
PAGE 22
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 90 80 70 60 Amplitude (V) 50 40 30 20 10 0 -10 -20 -30 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 Figure 11. IEC Clamping Waveforms 8 kV Contact (IEC ESD Pins) 30 20 10 0 Amplitude (V) -10 -20 -30 -40 -50 -60 -70 -80 -90 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 Figure 12.
PAGE 23
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) 0 Closest signals D2+ to D2Farthest signals D2+ to CLK+ D2+ to D2D2+ to CLK+ -20 S21 (dB) -40 -60 -80 -100 Tested with typical operating voltage -120 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 Frequency (Hz) Figure 13. Channel-to-Channel Crosstalk 1.00000 S21 -1.00000 Insertion Loss (dB) -3.00000 -5.00000 -7.00000 -9.00000 -11.00000 -13.00000 -15.00000 1.
PAGE 24
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 15. Eye Diagram Performance on a Test Board for the D+, D- Lines at 2.5 Gbps Figure 16. Eye Diagram Performance on a Test Board for the D+, D- Lines at 3.
PAGE 25
TPD12S015 www.ti.com SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 VCC Input 50% 50% 0V Output 70% 30% 70% 30% tf VCC VOL tr A. RT termination resistance should be equal to ZOUT of pulse generators. B. CL includes probe and jig capacitance. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLH and tPHL are the same as tpd.
PAGE 26
TPD12S015 SLLSE19E – DECEMBER 2009 – REVISED JUNE 2013 www.ti.com REVISION HISTORY Changes from Revision B (July 2010) to Revision C Page • Added Type D connecter specification to "FEATURES" ...................................................................................................... 1 • Added Type D connecter specification to "DESCRIPTION/ORDERING INFORMATION" ..................................................
PAGE 27
PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TPD12S015YFFR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFF 28 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SNAGCU Level-1-260C-UNLIM (4) -40 to 85 PN015 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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D: Max = 2.79 mm, Min = 2.73 mm E: Max = 1.59 mm, Min = 1.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.