Datasheet

TPD12S015A

www.ti.com

SLLSE74C –JUNE 2011–REVISED MARCH 2013

Figure 3. DDC/CEC Level Shifter Operation (B to A Direction)

Rise-Time Accelerators

The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on

the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of

the bus is releasing the signal.

Remark

Ground offset between the TPD12S015A ground and the ground of devices on port A of the TPD12S015A must

be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of

current at 0.4 V will have an output resistance of 133 ohms or less (R = E / I). Such a driver will share enough

current with the port A output pull-down of the TPD12S015A to be seen as a LOW as long as the ground offset is

zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILC can be as low

as 90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not

exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the port A of the TPD12S015A

as their output LOW levels will not be recognized by the TPD12S015A as a LOW. If the TPD12S015A is placed

in an application where the VIL of port A of the TPD12S015A does not go below its VILC it will pull port B LOW

initially when port A input transitions LOW but the port B will return HIGH, so it will not reproduce the port A input

on port B. Such applications should be avoided. Port B is interoperable with all I

C bus slaves, masters and

repeaters.

CEC Level Shift Operation

The CEC level shift function operates in the same manner as the DDC lines except that the CEC line does not

need the rise time accelerator function.

Internal Pullup Resistor

The TPD12S015A has incorporated all the required pullup and pulldown resistors at the interface pins. The

system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines. For

proper system operation no external resistors should be placed at the A and B ports. If there is internal pullups at

the host processor, they should be disabled.

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