Datasheet

300 mV
Port A
Port B
V
CCA
I
ACCEL
5VOUT
R
PUA
R
PUB
DDC Lines Only
ACCEL
Glitch
Filter
150 mV
CMP1
700 mV
CMP2
TPD12S015A
SLLSE74C –JUNE 2011–REVISED MARCH 2013 www.ti.com
APPLICATION INFORMATION
DDC/CEC Level Shift Circuit Operation
The TPD12S015A enables DDC translation from V
CCA
(system side) voltage levels to 5V (HDMI cable side)
voltage levels without degradation of system performance. The TPD12S015A contains two bidirectional open-
drain buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side
DDC-bus and the 5V DDC-bus. The port B I/Os are over-voltage tolerant to 5.5 V even when the device is
unpowered. After powerup and with the LS_OE and CT_CP_HPD pins high, a low level on port A (below
approximately V
ILC
= 0.08*V
CCA
V) turns the corresponding port B driver (either SDA or SCL) on and drives port
B down to V
OLB
V. When port A rises above approximately 0.10*VCCA V, the port B pulldown driver is turned off
and the internal pullup resistor pulls the pin high. When port B falls first and goes below 0.3*5VOUT, a CMOS
hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to approximately
V
OLA
= 0.16*V
CCA
V. The port B pulldown is not enabled unless the port A voltage goes below V
ILC
. If the port A
low voltage goes below V
ILC
, the port B pulldown driver is enabled until port A rises above (V
ILC
+ ΔV
T-HYSTA
),
then port B, if not externally driven LOW, will continue to rise being pulled up by the internal pullup resistor.
Figure 2. DDC/CEC Level Shifter Block Diagram
DDC/CEC Level Shifter Operational Notes for V
CCA
= 1.8 V
• The threshold of CMP1 is ~150mV +/- the 40mV of total hysteresis.
• The comparator will trip for a falling waveform at ~130mV
• The comparator will trip for a rising waveform at ~170mV
• To be recognized as a zero, the level at Port A must first go below 130mV (VILC in spec) and then stay below
170mV (VILA in spec)
• To be recognized as a one, the level at A must first go above 170mV and then stay above 130mV
• VILC is set to 110mV in Electrical Characteristics Table to give some margin to the 130mV
• VILA is set to 140mV in the Electrical Characteristics Table to give some margin to the 170mV
• VIHA is set to 70% of VCCA to be consistent with standard CMOS levels
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