Datasheet

TPD12S015A
www.ti.com SLLSE74C –JUNE 2011–REVISED MARCH 2013
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5V (continued)
V
CCA
= 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
t
f
A port fall time A Port DDC Channels Enabled 110
ns
B port fall time B Port 83
t
r
A port rise time A Port DDC Channels Enabled 190
ns
B port rise time B Port 92
f
MAX
Maximum switching frequency DDC Channels Enabled 400 kHz
Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5V
V
CCA
= 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay A to B CEC Channels Enabled 437
ns
B to A 267
t
PLH
A to B 13
μs
B to A 0.264
t
f
A port fall time A Port CEC Channels Enabled 110
ns
B port fall time B Port 96
t
r
A port rise time A Port CEC Channels Enabled 202 ns
B port rise time B Port 15 μs
Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5V
V
CCA
= 1.5 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay B to A CEC Channels Enabled 10
μs
t
PLH
B to A 9
t
f
A port fall time A Port CEC Channels Enabled 0.47 ns
t
r
A port rise time A Port CEC Channels Enabled 0.51 ns
Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8V
V
CCA
= 1.8 V
PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay A to B DDC Channels Enabled 334
B to A 229
ns
t
PLH
A to B 431
B to A 169
t
f
A port fall time A Port DDC Channels Enabled 94
ns
B port fall time B Port 83
t
r
A port rise time A Port DDC Channels Enabled 191
ns
B port rise time B Port 92
f
MAX
Maximum switching frequency DDC Channels Enabled 400 kHz
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPD12S015A