Datasheet

_
+
V
DD
V
O+
V
O−
GND
6
5
8
7
To Battery
C
s
IN−
IN+
4
3
R
I
R
I
40 kΩ
40 kΩ
+
−
C
I
C
I
(1)
C
(BYPASS)
is optional
Bias
Circuitry
2
SHUTDOWN
1
C
(BYPASS)
(1)
100 kΩ
IN
C
I
C
I
_
+
V
DD
V
O+
V
O−
GND
6
5
8
7
To Battery
C
s
IN−
IN+
4
3
R
I
R
I
40 kΩ
40 kΩ
(1)
C
(BYPASS)
is optional
Bias
Circuitry
2
SHUTDOWN
1
C
(BYPASS)
(1)
100 kΩ
TPA6211A1
SLOS367D –AUGUST 2003– REVISED JUNE 2011 www.ti.com
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
Figure 30. Single-Ended Input Application Schematic
14 Copyright © 2003–2011, Texas Instruments Incorporated