Datasheet

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ELECTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
(1) (2)
SCL
SDA
t
w(H)
t
w(L)
t
su1
t
h1
TPA6130A2
SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008
T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage V
DD
= 2.5 V to 5.5 V, inputs grounded 150 400 µ V
PSRR Power supply rejection ratio V
DD
= 2.5 V to 5.5 V, inputs grounded – 109 – 90 dB
CMRR Common mode rejection ratio V
DD
= 2.5 V to 5.5 V – 68 dB
SCL, SDA 1
|I
IH
| High-level input current V
DD
= 5.5 V, V
I
= V
DD
µA
SD 10
|I
IL
| Low-level input current V
DD
= 5.5 V, V
I
= 0 V SCL, SDA, SD 1 µA
V
DD
= 2.5 V to 5.5 V, SD = V
DD
4 6 mA
Shutdown mode, V
DD
= 2.5V to 5.5 V, SD = 0 V 0.4 1 µA
I
DD
Supply current
SW Shutdown mode, V
DD
= 2.5V to 5.5 V, SWS = 1 25 75 µA
Both HP amps disabled, V
DD
= 2.5V to 5.5 V,
1.4 2.5 mA
SWS = 0, Charge Pump enabled, SD = V
DD
For I
2
C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHz
t
w(H)
Pulse duration, SCL high 0.6 µ s
t
w(L)
Pulse duration, SCL low 1.3 µ s
t
su1
Setup time, SDA to SCL 300 ns
t
h1
Hold time, SCL to SDA 10 ns
t
(buf)
Bus free time between stop and start condition 1.3 µ s
t
su2
Setup time, SCL to start condition 0.6 µ s
t
h2
Hold time, start condition to SCL 0.6 µ s
t
su3
Setup time, SCL to stop condition 0.6 µ s
(1) V
Pull-up
= V
DD
(2) A pull-up resistor ≤ 2 k Ω is required for a 5 V I
2
C bus voltage.
Figure 1. SCL and SDA Timing
Copyright © 2006 – 2008, Texas Instruments Incorporated 5
Product Folder Link(s): TPA6130A2