Datasheet

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Combination of Single Byte Writes
D2Start ACK 01 ACK 00 ACK Stop
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
Data
(ControlRegister
)DATA1
D2Start ACK 09 ACK C0 ACK
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA2
Data
(ControlRegister
)DATA2
Stop
Single Byte Read
D2
Start
ACK
01
ACK Start
D3
XX
TPA5051 Addressand
Write
Register Address
(ControlRegister
)DATA1
Stop
ACK
DataRead
(ControlRegister
)DATA1
No
ACK
TPA5051 Addressand
Read
TPA5051
SLOS497A – JUNE 2006 – REVISED JULY 2006
In this example, DATA1 set to operate in the I
2
S mode, and DATA2 is set to mute.
Note that in every circumstance where a delay or stream type is written into the memory of the TPA5051, a 1
must be written to the Complete Update registers for the change to take effect. In this example, the stream type
change made to DATA1 would not take effect. This does not apply to muting, which occurs in the Control
registers.
In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by is
read by the master device, the master device issues a Not Acknowledge, before stopping the communication.
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