Datasheet

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PIN DESCRIPTIONS
BCLK DATA_OUT GND VDD
ADD1
LRCLK
SCL
GND
ADD0
ADD2
GND
DATA
7
5
6
11
9
10
12
16
15
14
13
3
1
2
4
SDA
8
GND GND
GND
RSA (QFN)PACKAGE
(TOP VIEW)
FUNCTIONAL BLOCK DIAGRAM
DATA
BCLK
LRCLK
INPUT
BUFFER
OUTPUT
BUFFER
DATA_OUT
CONTROL
2
3
I C
2
ADDx(2:0)
DELAY
MEMORY
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
ADD0 10 I I
2
C address select pin – LSB
ADD1 11 I I
2
C address select pin
ADD2 12 I I
2
C address select pin – MSB
BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input.
DATA 2 I Audio serial data input for serial input. 5V tolerant input.
DATA_OUT 15 O Delayed audio serial data output.
GND 5–9, 14 P Ground – All ground terminals must be tied to GND for proper operation
LRCLK 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input.
SCL 3 I I
2
C communication bus clock input. 5V tolerant input.
SDA 4 I/O I
2
C communication bus data input. 5V tolerant input.
VDD 13 P Power supply interface.
Connect to ground. Must be soldered down in all applications to properly secure device on the
Thermal Pad -
PCB.
2
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