Datasheet

www.ti.com
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I
2
CDeviceAddressand
Read/WriteBit
Register DataByte
D7 D6 D1 D0 ACK
I
2
CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6 A0 ACK
Acknowledge
I
2
CDeviceAddressand
Read/WriteBit
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I
2
CDeviceAddressand
Read/WriteBit
Register
OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
TPA5050 Operation
VDD
DATA
LRCLK
BCLK
GND
DATA_OUT
SDA
SCL
ADD0
ADD1
ADD2
GND
3.3V
0.1 Fm
Digital Audio
WordClock
BitClock
Delayed Audio
I CClock
2
I CData
2
I C Address
Select
2
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Figure 8. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA5050 to the master device as shown in Figure 9 . With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 9. Multiple-Byte Read Transfer
The following sections describe the registers configurable via I
2
C commands for the TPA5050.
Only a single decoupling capacitor (0.1 µ F–1 µ F) is required across VDD and GND. The ADDx terminals can be
directly connected to VDD or GND. Table 1 describes the I
2
C addresses selectable via the ADDx terminals. A
schematic implementation of the TPA5050 is shown in Figure 10 .
Figure 10. TPA5050 Schematic
9
Submit Documentation Feedback