Datasheet

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APPLICATION EXAMPLES
Single Byte Write
D2Start ACK 01 ACK C0 ACK Stop
TPA5050 Addressand
Write
Register Address Data
Multiple Byte Write
D2Start
ACK
01
00
0F
ACK
Stop
TPA5050 Addressand
Write
Register Address
(ControlRegister)
Data
(RightDelayUpperBits)
ACK
ACK
FF
ACK
Data
(ControlRegister)
Data
(RightDelayLowerBits)
10
ACK
00
00
00
ACK
Data
(LeftDelayUpperBits)
Data
(RJPacket=0Bits)
ACK
ACK
01
ACK
Data
(FrameDelay)
Data
(CompleteUpdate)
Data
(LeftDelayLowerBits)
Combination Single Byte Write and Sequential Write
D2
Start ACK 01 ACK 01 ACK Stop
TPA5050 Addressand
Write
Register Address
(ControlRegister)
Data
(ControlRegister)
D2Start ACK 06 ACK 91 ACK 10
TPA5050 Addressand
Write
Register Address
(FrameDelay)
Data
(FrameDelay)
01
ACK
Data
(RJPacket=16Bits)
Stop
Data
(CompleteUpdate)
ACK
TPA5050
SLOS492B – MAY 2006 – REVISED MAY 2007
Table 7. Complete Update Registers (0x08)
(1)
D7–D1 D0 FUNCTION
X 0 No data from the register settings is passed to the delay block.
X 1 Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
(1) Default values are in bold.
The following are some examples of I
2
C commands used to read or write to the TPA5050. For all conditions,
assume the address of the TPA5050 is set to 001.
In this example, the TPA5050 is set to mute both left and right channels, and to operate in I
2
S mode.
In this example, the TPA5050 is set to make both the left and right channels active, operate in I
2
S mode, delay
the right channel by 4095 samples, and delay the left channel by 4096 samples. This is a sequential write, so all
registers must have data written to them.
In this example, the TPA5050 is set to operate in the Right Justified mode, with a packet length of 16 bits. The
device is to delay the audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs)
= 48 kHz, and the Frame rate = 50 Hz. This is a combination of single writes and a sequential write. Since the
Right Justified mode is set in the Control Register, and the Frame Delay is set in register 0x06, the data in
registers 0x02–0x05 can be ignored.
Note that in every circumstance where a delay was written into the memory of the TPA5050, a 1 must be written
to the Complete Data register for the change to take effect. This does not apply to muting, which occurs in the
Control register.
12
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