Datasheet

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11
PVCCL
SD
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
TPA3125D2
SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DUAL INLINE PACKAGE
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
20-PIN
NAME
(DIP)
PVCCL 1 Power supply for left channel H-bridge.
Shutdown signal for IC (low = outputs disabled, high = operational). TTL logic levels with
SD 2 I
compliance to AVCC.
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
MUTE 3 I
outputs enabled). TTL logic levels with compliance to AVCC.
LIN 4 I Audio input for left channel.
RIN 5 I Audio input for right channel.
Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 6 O
external capacitor sizing.
AGND 7 Analog ground for digital/analog cells in core.
AGND 8 Analog ground for digital/analog cells in core.
VCLAMP 9 Internally generated voltage supply for bootstrap capacitors.
PVCCR 10 Power supply for right channel H-bridge.
PGNDR 11 Power ground for right channel H-bridge.
ROUT 12 O Class-D H-bridge negative output for right channel.
BSR 13 I Bootstrap input for right channel.
GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL .
BSL 18 I Bootstrap input for left channel.
LOUT 19 O Class-D H-bridge positive output for left channel.
PGNDL 20 Power ground for left channel H-bridge.
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