Datasheet
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PVCCL
SD
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
TPA3122D2
SLOS527A – DECEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
N (DIP) PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
20-PIN
NAME
(DIP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC.
RIN 5 I Audio input for right channel.
LIN 4 I Audio input for left channel.
GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
MUTE 3 I
outputs enabled). TTL logic levels with compliance to AVCC.
BSL 18 I/O Bootstrap I/O for left channel.
PVCCL 1 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
LOUT 19 O Class-D -H-bridge positive output for left channel.
PGNDL 20 Power ground for left channel H-bridge.
VCLAMP 9 Internally generated voltage supply for bootstrap capacitors.
BSR 13 I/O Bootstrap I/O for right channel.
ROUT 12 O Class-D -H-bridge negative output for right channel.
PGNDR 11 Power ground for right channel H-bridge.
PVCCR 10 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
AGND 8 Analog ground for digital/analog cells in core.
AGND 7 Analog Ground for analog cells in core.
Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 6 O
external capacitor sizing.
AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
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