Datasheet

PWM
Logic
Gate
Drive
Gate
Drive
PVCCL
PVCCL
GVDD
PVCCL
PVCCL
BSPL
PGND
OUTPL
OUTNL
PGND
GVDD
BSNL
PWM
Logic
Gate
Drive
Gate
Drive
PVCCL
PVCCL
GVDD
PVCCL
PVCCL
BSNR
PGND
OUTNR
OUTPR
PGND
GVDD
BSPR
LINP
LINN
RINP
RINN
UVLO/OVLO
SC Detect
DC Detect
Thermal
Detect
Startup Protection
Logic
Biases and
References
FAULT
SD
GAIN0
PLIMIT
AGND
AVCC
GAIN1
Gain
Control
TTL
Buffer
Ramp
Generator
AVDD
GVDD
GVDD
LDO
Regulator
Gain
Control
PLIMIT
PLIMIT
Reference
PBTL
Gain
Control
TTL
Buffer
PBTL
Select
PBTL Select
PBTL Select
OUTPL FB
OUTNL FB
OUTNN FB
OUTNP FB
OUTPR FB
OUTNR FB
OUTNL FB
OUTPL FB
PLIMIT
TPA3113D2
SLOS650E –AUGUST 2009–REVISED JULY 2012 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
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