Datasheet

PWM
Logic
Gate
Drive
PVCC
PVCC
GVDD
BSP
PGND
OUTP
Gate
Drive
PVCC
PVCC
GVDD
BSN
PGND
OUTN
INP
INN
UVLO/OVLO
SC Detect
DC Detect
Thermal
Detect
Startup Protection
Logic
Biases and
References
FAULT
SD
GAIN0
PLIMIT
AGND
AVCC
GAIN1
Gain
Control
TTL
Buffer
Ramp
Generator
AVDD
GVDD
GVDD
LDO
Regulator
Gain
Control
PLIMIT
PLIMIT
Reference
OUTP FB
OUTN FB
OUTN FB
OUTP FB
TPA3111D1
SLOS618E –AUGUST 2009–REVISED AUGUST 2012 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
6 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Links: TPA3111D1