Datasheet

TPA3111D1
www.ti.com SLOS618E –AUGUST 2009–REVISED AUGUST 2012
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
The TPA3111D1 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are very fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220 μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3111D1 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1000 pF and a larger mid-freqency cap of value between 0.1 µF and 1 µF also of good quality to
the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Output filter—The ferrite EMI filter (Figure 21) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 19 and Figure 20) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0.33 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. . See TI Application Report
SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB footprints, see
mechanical pages appended to the end of this data sheet.
For an example layout, see the TPA3111D1 Evaluation Module (TPA3111D1EVM) User Manual. Both the EVM
user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com.
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REVISION HISTORY
Changes from Original (August 2009) to Revision A Page
• Added slew rate adjustment information ............................................................................................................................. 10
Changes from Revision A (July 2010) to Revision B Page
• Replaced the Dissipations Ratings Table with the Thermal Information Table .................................................................... 2
• In the BSN and BSP CAPACITORS section, the 220-nf capacitor rated for at least 25V was changed to a 470-nf
capacitor rated to at least 16V ............................................................................................................................................ 18
Changes from Revision B (August 2010) to Revision C Page
• Added < 10 V/ms to V
I
in the Absolute Maximum Ratings table .......................................................................................... 2
Changes from Revision C (October 2010) to Revision D Page
• Added a 100kΩ resistor to AVCC Pin 14 and Note 1 to Figure 17 .................................................................................... 13
Changes from Revision D (July 2012) to Revision E Page
• Changed 0.1 mF to 0.1 µF and 200 mF 200 µF in the POWER SUPPLY DECOUPLING, C
S
section ............................. 18
• Changed 0.1 mF and 1 mF to 0.1 µF and 1 µF in the PRINTED-CIRCUIT BOARD (PCB) LAYOUT section .................. 19
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