Datasheet

TPA3110D2
www.ti.com SLOS528D –JULY 2009–REVISED JULY 2012
PIN FUNCTIONS
PIN
I/O/P DESCRIPTION
NAME NUMBER
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
SD 1 I
with compliance to AVCC.
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC.
FAULT 2 O Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both
short circuit faults and dc detect faults must be reset by cycling PVCC.
LINP 3 I Positive audio input for left channel. Biased at 3V.
LINN 4 I Negative audio input for left channel. Biased at 3V.
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
AVCC 7 P Analog supply
AGND 8 Analog signal ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for PLIMIT
GVDD 9 O
function
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect
PLIMIT 10 I
directly to GVDD for no power limit.
RINN 11 I Negative audio input for right channel. Biased at 3V.
RINP 12 I Positive audio input for right channel. Biased at 3V.
NC 13 Not connected
PBTL 14 I Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
PVCCR 15 P
connect internally.
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
PVCCR 16 P
connect internally.
BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.
OUTPR 18 O Class-D H-bridge positive output for right channel.
PGND 19 Power ground for the H-bridges.
OUTNR 20 O Class-D H-bridge negative output for right channel.
BSNR 21 I Bootstrap I/O for right channel, negative high-side FET.
BSNL 22 I Bootstrap I/O for left channel, negative high-side FET.
OUTNL 23 O Class-D H-bridge negative output for left channel.
PGND 24 Power ground for the H-bridges.
OUTPL 25 O Class-D H-bridge positive output for left channel.
BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect
PVCCL 27 P
internally.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect
PVCCL 28 P
internally.
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