Datasheet

Biases
&
References
TTL InputBuffer
(VCCCompliant)
Startup
Protection
Logic
VREGok
INP
INN
Ramp
Generator
ROSC
VCCok
4VReg
AVCC
VREG
PWM
Logic
Gain
Control
SHUTDOWN
VBYP
MSTR/SLV
SYNC
AVCC
AVCC
AVCC
Gain
Control
GAIN0
GAIN1
4
ToGain Adj.
Blocks&
StartupLogic
MUTE
FAULT
VREG
AGND
VBYP
VBYP
VREG
VBYP
VClamp
Gen
PVCC
Gate
Drive
Gate
Drive
TTL InputBuffer
(VREG
Compliant)
Thermal
SC
Detect
PVCC
BSN
VCLAMP
PVCC
PVCC
OUTN
BSP
OUTP
PGND
GainControl
GainControl
TPA3106D1
SLOS516C –OCTOBER 2007–REVISED AUGUST 2010 www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is
MSTR/SLV 7 I an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV
SYNC 8 I/O
terminal. Input signal not to exceed VREG.
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor
VBYP 11 O
sizing.
4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not specified for
VREG 10 O
driving other external circuitry.
AVCC 32 High-voltage analog power supply. Not internally connected to PVCCL.
Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to
AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an
Thermal Pad — —
internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the
PCB for mechanical reliability.
FUNCTIONAL BLOCK DIAGRAM
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