Datasheet

Biases
and
References
Startup
Protection
Logic
VREGok
RINP
RINN
Ramp
Generator
ROSC
VCCok
4VReg
AVCC
VREG
PWM
Logic
Gain
Control
Gain
Control
LINP
LINN
SHUTDOWN
VBYP
VBYP
MSTR/SLV
PWM
Logic
SYNC
AVCC
AVCC
AVCC
Gain
Control
GAIN0
GAIN1
8
ToGain Adj.
Blocksand
StartupLogic
MUTE
FAULT
VREG
AGND
VBYP
VBYP
VREG
VBYP
VClamp
Gen
PVCCR
Gate
Drive
Gate
Drive
VClamp
Gen
Gate
Drive
Thermal
SC
Detect
PVCCR
Gate
Drive
BSLN
VCLAMPL
PVCCL
PVCCL
BSLP
LOUTN
BSRN
VCLAMPR
PVCCR
PVCCR
ROUTN
BSRP
ROUTP
PGNDR
PVCCL
PVCCL
PGNDL
LOUTP
Gain
Gain
Gain
Gain
TLL Input
Buffer
(VCCCompliant)
TLL Input
Buffer
(VCCCompliant)
TPA3100D2
www.ti.com SLOS469F –OCTOBER 2005–REVISED AUGUST 2010
FUNCTIONAL BLOCK DIAGRAM
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
(1)
FIGURE
THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4
THD+N Total harmonic distortion + noise vs Output power 5, 6, 7, 8
Closed-loop response vs Frequency 9, 10
Output power vs Supply voltage 11. 12
Efficiency vs Output power 13, 14
V
CC
Supply current vs Total output power 15, 16
Crosstalk vs Frequency 17, 18
k
SVR
Supply ripple rejection ratio vs Frequency 19, 20
(1) All graphs were measured using the TPA3100D2 EVM.
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