Datasheet

Biases
&
References
TTL Input
Buffer
Startup
Protection
Logic
OC
Detect
Thermal
VDDok
RINP
RINN
VAROUTR
Ramp
Generator
COSC
ROSC
VCCok
5V LDO
AVCC
AVDD
AVDD
VDD
Deglitch &
Modulation
Logic
Gain
Adj.
Rfdbk2
Rfdbk2
Cint2
Cint2
Gain
Control
Deglitch &
Modulation
Logic
Gain
Adj.
Rfdbk2
Rfdbk2
Cint2
Cint2
LINP
LINN
VAROUTL
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSRP
PVCCR(2)
ROUTP(2)
PGNDR
PGNDR
ROUTN(2)
PVCCR(2)
BSRN
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSLP
PVCCL(2)
LOUTP(2)
PGNDL
PGNDL
LOUTN(2)
PVCCL(2)
BSLN
VCLAMPL
VCLAMPR
VOLUME
VARDIFF
VARMAX
To Gain Adj.
Blocks
SD
VREF
REFGND
V2P5
V2P5
V2P5
Mode
Control
MODE
MODE_OUT
AVCC
AGND
AVDDREF
Gain
Adj.
Gain
Adj.
V2P5
V2P5
V2P5
V2P5
FADE
TPA3004D2
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FUNCTIONAL BLOCK DIAGRAM
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