Datasheet

SCL
SDA
t
h2
t
(buf)
t
su2
t
su3
StartCondition
StopCondition
SCL
SDA
t
w(H)
t
w(L)
t
su1
t
h1
TPA2028D1
SLOS660B –JANUARY 2010–REVISED SEPTEMBER 2012 www.ti.com
I
2
C TIMING CHARACTERISTICS
For I
2
C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHz
t
W(H)
Pulse duration, SCL high 0.6 μs
t
W(L)
Pulse duration, SCL low 1.3 μs
t
SU(1)
Setup time, SDA to SCL 100 ns
t
h1
Hold time, SCL to SDA 10 ns
t
(buf)
Bus free time between stop and start 1.3 μs
condition
t
SU2
Setup time, SCL to start condition 0.6 μs
t
h2
Hold time, start condition to SCL 0.6 μs
t
SU3
Setup time, SCL to stop condition 0.6 μs
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
6 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPA2028D1