Datasheet

A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I
2
CDeviceAddressand
Read/WriteBit
Register DataByte
D7 D6 D1 D0 ACK
I
2
CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
Register
A6 A5 A4 A3 A2 A1 A0
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I
2
CDeviceAddressand
Read/WriteBit
Register DataByte
TPA2028D1
www.ti.com SLOS660B –JANUARY 2010–REVISED SEPTEMBER 2012
SINGLE-BYTE WRITE
As Figure 41 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to '0'. After receiving the correct I
2
C device
address and the read/write bit, the TPA2028D1 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA2028D1 internal memory address being accessed. After receiving the
register byte, the TPA2028D1 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2028D1
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Figure 41. Single-Byte Write Transfer
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA2028D1 as shown in Figure 42. After receiving each data byte,
the TPA2028D1 responds with an acknowledge bit.
Figure 42. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As Figure 43 shows, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I
2
C device address and the read/write bit. For the data read transfer, both a write followed by a
read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a '0'.
After receiving the TPA2028D1 address and the read/write bit, the TPA2028D1 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA2028D1 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2028D1 address and
the read/write bit again. This time the read/write bit is set to '1', indicating a read transfer. Next, the TPA2028D1
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 43. Single-Byte Read Transfer
Copyright © 2010–2012, Texas Instruments Incorporated 23
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