Datasheet

TPA0202
2-W STEREO AUDIO POWER AMPLIFIER
SLOS205B – FEBRUARY 1998 – REVISED DECEMBER 2000
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
50 kΩ
BYPASS
V
DD
100 kΩ
100 kΩ
Figure 64. PNP Transistor Clamping of BYPASS Terminal
The PNP transistor limits the voltage drop across the 50 kΩ resistor by slewing the internal node slowly when
power is applied. At start-up, the xBYPASS capacitor is at 0. The PNP is pulling the mid-point of the bias circuit
down, so the capacitor sees a lower effective voltage, and thus charges slower. This appears as a linear ramp
(while the PNP transistor is conducting), followed by the expected exponential ramp of an R-C circuit.
If the expression in equation 10 cannot be fulfilled or the small amount of pop is still unacceptable for the
application, then external circuitry must be added that can eliminate the pop heard during power up and while
transitioning out of mute or shutdown modes.
By holding the device in SE mode when the pop normally occurs, no pop can be heard through the
BTL-connected speakers (as the negative output is in a high impedance state when the amplifier is in SE mode).
From a hardware point of view, the easiest way to implement this is to drive the SE/BTL terminal from the
general-purpose input-output (GPIO) in the system. If the SE/BTL terminal is normally connected to a
headphone socket (as shown in Figure 65), then the GPIO signal must either be taken through an OR gate (see
Figure 65) or isolated with a diode (any signal diode) (see Figure 66).
R
m2
100 kΩ
R
m1
100 kΩ
V
DD
Left
Channel
From GPIO
Right
Channel
SE/BTL
0.1 µF
Figure 65. Implementation with an OR Gate