Datasheet

Reference
2-12
Operation
2.5.3.2 Gain Register Operation
The gain of the TPA0172 ranges from +20 dB to –60 dB in 64 1.25 dB steps.
At power up, both the right and left channels are set at –60dB. The truth table
shown in Table 2–8 gives examples of valid values that may be read from or
written to the four gain setting registers. Note that the amplifier is muted if either
bit 7 or bit 6 is set. Furthermore, to avoid any unwanted clicks or pops, the gain
settings should not be changed until the amplifier has completed the power-up
sequence, which can be determined by monitoring bit 7 of the mask register.
When the bit goes to 0, the power-up sequence is complete
Table 2–8. TPA0172 Gain Settings Truth Table
GAIN
(dB)
BIT 7
(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
(LSB)
20 0 0 0 0 0 0 0 0
18.75 0 0 0 0 0 0 0 1
17.5 0 0 0 0 0 0 1 0
16.25 0 0 0 0 0 0 1 1
... ... ... ... ... ... ... ... ...
–57.5 0 0 1 1 1 1 0 1
–58.75 0 0 1 1 1 1 1 0
–60 0 0 1 1 1 1 1 1
–85
(mute)
1 1 X X X X X X
2.5.3.3 Mask Register Operation
The mask register allows the user to select whether SHUTDOWN, SE/BTL,
and PCBEEP are to be controlled by the external pins or by the internal control
register. Since PCBEEP does not have an external control pin available,
writing a 1 to this bit will disable all internal register control and place the
PCBEEP in auto-detect mode. When a bit is set, the corresponding internal
control register bit is masked or ignored, and the external pin controls the
operating mode. Conversely, when a bit is set to 0, the corresponding external
pin is disabled and the internal control register bit determines the operating
mode. For example, writing XXXXX110 to the register allows a PCBEEP input
to be automatically detected and the external pin to control SE/BTL, while
allowing the control register to control SHUTDOWN.
The MSB of the mask register is read only. It is set when the TPA0172 is
executing its power-up sequence and is set to 0 upon completion of the
sequence and during normal operation. To avoid any unwanted clicks or pops,
the gain registers should not be changed while this bit is set.