Datasheet

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NRND

TP3404

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SNOS703 –DECEMBER 2004

Table 2. Per Line Control Register Address Map

Byte 1

Function MSB Nibble

(2)

LSB Nibble Byte 2

(1)

7 6 5 4 3 2 1 0

Write TSXD Register N 0 0 0 0 See Table 5

Read TSXD Register N 0 0 0 1 See Table 5

Write TSXB1 Register N 0 0 1 0 See Table 4

Read TSXB1 Register N 0 0 1 1 See Table 4

Write TSXB2 Register N 0 1 0 0 See Table 4

Read TSXB2 Register N 0 1 0 1 See Table 4

Write TSRD Register N 0 1 1 0 See Table 5

Read TSRD Register N 0 1 1 1 See Table 5

Write TSRB1 Register N 1 0 0 0 See Table 4

Read TSRB1 Register N 1 0 0 1 See Table 4

Write TSRB2 Register N 1 0 1 0 See Table 4

Read TSRB2 Register N 1 0 1 1 See Table 4

Write Line Control Register (CTR L) N 1 1 1 0 See Table 3

Read Line Control Register (CTRL) N 1 1 1 1 See Table 3

(1) Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins.

(2) N = 0, 1, 2, or 3 in straight Binary notation for Line 0, 1, 2, or 3 respectively.

LINE CONTROL REGISTERS CTRLN

Each of the 4 transceivers has a Line Control Register, CTRL0–CTRL3, which provides for control of loop

activation, Ioopbacks, Interrupt enabling and D channel interface enabling. Table 3 lists the functions.

POWER ON INITIALIZATION

Following the initial application of power, the QDASL enters the power-down (de-activated) state, in which all the

internal circuits are inactive and in a low power state except for a Line-Signal Detect Circuit for each of the 4

lines, and the necessary bias circuits. The 4 line outputs, Lo0–Lo3, are in a high impedance state and all digital

outputs are inactive. All bits in the Line Control Registers power-up initially set to “0”. While powered-down, each

Line-Signal Detect Circuit continually monitors its line, to detect if the far-end initiates loop transmission.

POWER-UP/DOWN CONTROL

To power-up the device and initiate activation, bit C7 in any of the 4 Line Control Registers must be set high, see

Table 3. Setting C7 low de-activates the loop, or puts the channel in power-down state. During power-down

state, internal register data is retained, and still can be accessed.

LOOPBACKS

Four different loopbacks can be set for each line. They are enabled and disabled by setting the corresponding

bits in the Control Register, see Table 3. In addition, a line must be activated to see the effect of loopback

commands.

1. 2B+D Line Loopback

– When bit 5 is set to 1, this loop will transfer all three channels, B1, B2 and D, that are received at the Li

pin back to the Lo pin. Data out on BO/DO is still the same as received at the Li input.

2. B1 Line Loopback

– When bit 4 is set high, the loop path is the same as (1) but only data on the B1 channel is looped back to

the line. Transmit data in the B2 and D channels is from the Bi/DI pins.

3. B2 Line Loopback

– As (2) but for the B2 channel.

4. 2B+D Digital Loopback

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