Datasheet
NRND
TP3404
www.ti.com
SNOS703 –DECEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, limits printed in BOLD characters are specified for V
CCA
= V
CCD
= 5V ±5%, T
A
= 0°C to +70°C.
Typical characteristics are specified at V
DDA
= V
DDD
= 5.0V, T
A
= 25°C. All signals are referenced to GND, which is the
common of GNDA and GNDD
Symbol Parameter Conditions Min Typ Max Units
DIGITAL INTERFACE TIMING
f
BCLK
BCLK Frequency 4.096 4.1 MHz
t
WBH
, Clock Pulse Width High Measured from V
IH
to V
IH
70 ns
t
WBL
and Low for BCLK Measured from V
IL
to V
IL
70
t
RB
, Rise Time and Fall Time Measured from V
IL
to V
IH
15 ns
t
FB
of BCLK Measured from V
IH
to V
IL
15
t
HBM
BCLK Transition to MCLK High or Low −30 30 ns
t
SFC
Set up Time, FS Valid to BCLK Invalid 20 4 ns
t
HCF
Hold Time, BCLK Low to FS Invalid 40 30 ns
t
SBC
Setup Time, BI Valid to BCLK Invalid 30 11 ns
t
HCB
Hold Time, BCLK Valid to BI Invalid 40 7 ns
t
SDC
Setup Time, DI Valid to BCLK Low 30 ns
t
HCD
Hold Time, BCLK Low to DI Invalid 40 ns
t
DCB
Delay Time, BCLK High to BO Valid Load = 2 LSTTL + 100 pF 80 ns
t
DCBZ
Delay Time, BCLK Low to BO High-Z 80 120 ns
t
DCD
Delay Time, BCLK High to DO valid Load = 2 LSTTL + 100 pF 80 ns
t
DCZ
Delay Time, BCLK Low to DO High Impedance 40 120 ns
t
DCT
Delay Time, BCLK High to TSB Low 120 ns
t
ZBT
Disable Time, BCLK Low to TSB High-Z 120 ns
MICROWIRE CONTROL INTERFACE TIMING
f
CCLK
Frequency of CCLK 2.1 MHz
t
CH
Period of CCLK High Measured from V
IH
to V
IH
150 ns
t
CL
Period of CCLK Low Measured from V
IL
to V
IL
150 ns
t
SSC
Setup Time, CS Low to CCLK High 50 ns
t
HCS
Hold Time, CCLK High to CS Transition 40 ns
t
SIC
Setup Time, CI Valid to CCLK High 50 ns
t
HCI
Hold Time, CCLK High to CI Invalid 20 ns
t
DCO
Delay Time, CCLK Low to CO Valid 80 ns
t
DSOZ
Delay Time, CS High to CO High-Z 80 ns
t
DCIZ
Delay Time, CCLK to INT High-Z 100 ns
Copyright © 2004, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TP3404