Datasheet

NRND
TP3404
SNOS703 –DECEMBER 2004 www.ti.com
– This loop will transfer all data (2B+D) received at BI/DI back to BO/DO. The data is also transmitted to the
line.
TIME-SLOT ASSIGNMENT
The digital interface of the QDASL uses time-division multiplexing, with data framed in up to 64 possible 8-bit
time-slots per 125 μs frame. Channels B1 and B2 for all 4 lines are clocked in (towards the line) at the BI pin and
clocked out (from the line) at the BO pin. A separate port is provided for the D channel data for all 4 lines, which
is clocked in on DI and out on DO. In addition to time-slot assignment, D channel data may be assigned into 2-bit
sub-slots within each time slot, with up to 256 sub-slots per frame (with BCLK = 4.096 MHz). Each frame starts
with the first positive edge of BCLK after the FS signal goes high, and counting of timeslots starts from zero at
the beginning of the frame. Figure 5 shows the timing, with some example time-slot assignments.
For each of the 4 QDASL lines there are 6 Time-Slot Assignment control registers, one each for transmit and
receive B1, B2 and D channels. Selection of time-slots for transmit data into the BI or DI pin is made by writing
the timeslot number (in Hex notation) into the appropriate TSX register. TSXB1 is the time-slot assignment for
the transmit B1, TSXB2 is the time-slot assignment register for the transmit B2 channel and TSXD is the sub-slot
assignment register for the transmit D channel.
Table 3. Byte 2 of Control Register (CTRLN)
Bit Number Function
7 6 5 4 3 2 1 0
0 Deactivate Line
1 Activate Line
0 Disable Digital Loopback
1 Enable 2B+D Digital Loopback
0 Disable Line Loopback
1 Enable 2B+D Line Loopback
0 Disable B1 Line Loopback
1 Enable B1 Line Loopback
0 Disable B2 Line Loopback
1 Enable B2 Line Loopback
0 Disable Interrupt from this Line
1 Enable Interrupt from this Line
0 D Channel enabled from DO to Line
1 D Channel disabled from DO to Line
0 D Channel enabled from Line to DI
1 D Channel disabled from Line to DI
In the same manner the time-slot number should be written into the appropriate TSR registers for receive data at
the BO and DO pins. TSRB1 is the time-slot assignment for the receive B1 channel, TSRB2 is the time-slot
assignment register for the receive B2 channel and TSRD is the sub-slot assignment register for the receive D
channel.
Whenever any receive time-slot is active at BO, the TSB output is also pulled low.
REGISTERS TSXB1, TSXB2, TSRB1, TSRB2
The data format for all B channel time-slot assignment registers is shown in Table 4.
BIT 7 TRANSPARENCY CONTROL: EB
This bit enables or disables data transparency between the digital interface and the line interface for the selected
channel.
EB = 0 disables the channel.
EB = 1 enables the channel.
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