Datasheet

Definitions and Timing Conventions
DEFINITIONS
V
IH
V
IH
is the D.C. input level above which
an input level is guaranteed to appear as
a logical one. This parameter is to be
measured by performing a functional
test at reduced clock speeds and nomi-
nal timing, (i.e., not minimum setup and
hold times or output strobes), with the
high level of all driving signals set to V
IH
and maximum supply voltages applied
to the device.
V
IL
V
IL
is the D.C. input level below which
an input level is guaranteed to appear as
a logical zero to the device. This param-
eter is measured in the same manner as
V
IH
but with all driving signal low levels
set to V
IL
and minimum supply voltages
applied to the device.
V
OH
V
OH
is the minimum D.C. output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
V
OL
V
OL
is the maximum D.C. output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
Threshold Region The threshold region is the range of in-
put voltages between V
IL
and V
IH
.
Valid Signal A signal is Valid if it is in one of the valid
logic states. (i.e., above V
IH
or below
V
IL
). In timing specifications, a signal is
deemed valid at the instant it enters a
valid state.
Invalid signal A signal is invalid if it is not in a valid
logic state, i.e., when it is in the thresh-
old region between V
IL
and V
IH
. In timing
specifications, a signal is deemed In-
valid at the instant it enters the threshold
region.
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply.
Input Signals All input signals may be characterized
as: V
L
=
0.4V, V
H
=
2.4V, t
R
<
10 ns, t
F
<
10 ns.
Period The period of the clock signal is desig-
nated as t
Pxx
where
xx
represents the
mnemonic of the clock signal being
specified.
Rise Time Rise times are designated as t
Ryy
, where
yy represents a mnemonic of the signal
whose rise time is being specified. t
Ryy
is
measured from V
IL
to V
IH
.
Fall Time Fall times are designated as t
Fyy
, where
yy represents a mnemonic of the signal
whose fall time is being specified. t
Fyy
is
measured from V
IH
to V
IL
.
Pulse Width High The high pulse width width is designated
as t
WzzH
, where zz represents the mne-
monic of the input or output signal whose
pulse width is being specified. High
pulse widths are measured from V
IH
to
V
IH
.
Pulse Width Low The low pulse width is designated as
t
WzzL
, where zz represents the mne-
monic of the input or output signal whose
pulse width is being specified. Low pulse
widths are measured from V
IL
to V
IL
.
Setup Time Setup times are designated as t
Swwxx
,
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or strobe
input represented by mnemonic xx.
Setup times are measured from the ww
Valid to xx Invalid.
Hold Time Hold times are designated as T
Hwwxx
,
where ww represents the mnemonic of
the input signal whose hold time is being
specified relative to a clock or strobe in-
put represented by the mnemonic xx.
Hold times are measured from xx Valid
to ww Invalid.
Delay Time Delay times are designated as
T
Dxxyy
[ IHIL], where xx represents the
mnemonic of the input reference signal
and yy represents the mnemonic of the
output signal whose timing is being
specified relative to xx. The mnemonic
may optionally be terminated by an H or
L to specify the high going or low going
transition of the output signal. Maximum
delay times are measured from xx Valid
to yy Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the load
conditions specified in the Conditions
column of the Timing Specifications sec-
tion of this datasheet.
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