Datasheet
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
CC
ea
5.0V
g
5%, V
BB
eb
5.0V
g
5%, T
A
e
0
§
Cto70
§
C by correlation with 100% electrical testing at T
A
e
25
§
C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at V
CC
e
a
5.0V, V
BB
eb
5.0V, T
A
e
25
§
C. All timing parameters are measured at V
OH
e
2.0V and V
OL
e
0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol Parameter Conditions Min Typ Max Units
1/t
PM
Frequency of Master Clock 1.536 MHz
1.544 MHz
MCLK
X
and MCLK
R
2.048 MHz
t
RM
Rise Time of Master Clock MCLK
X
and MCLK
R
50 ns
t
FM
Fall Time of Master Clock MCLK
X
and MCLK
R
50 ns
t
PB
Period Bit of Clock 485 488 15725 ns
t
RB
Rise Time of Bit Clock BCLK
X
and BCLK
R
50 ns
t
FB
Fall Time of Bit Clock BCLK
X
and BCLK
R
50 ns
t
WMH
Width of Master Clock High MCLK
X
and MCLK
R
160 ns
t
WML
Width of Master Clock Low MCLK
X
and MCLK
R
160 ns
t
SBFM
Set-Up Time from BCLK
X
High 100 ns
to MCLK
X
Falling Edge
t
SFFM
Set-Up Time from FS
X
High Long Frame Only 100 ns
to MCLK
X
Falling Edge
t
WBH
Width of Bit Clock High 160 ns
t
WBL
Width of Bit Clock Low 160 ns
t
HBFL
Holding Time from Bit Clock Long Frame Only 0 ns
Low to Frame Sync
t
HBFS
Holding Time from Bit Clock Short Frame Only 0 ns
High to Frame Sync
t
SFB
Set-Up Time for Frame Sync Long Frame Only 80 ns
to Bit Clock Low
t
DBD
Delay Time from BCLK
X
High Load
e
150 pF plus 2 LSTTL Loads 0 180 ns
to Data Valid
t
DBTS
Delay Time to TS
X
Low Load
e
150 pF plus 2 LSTTL Loads 140 ns
t
DZC
Delay Time from BCLK
X
Low to 50 165 ns
Data Output Disabled
t
DZF
Delay Time to Valid Data from C
L
e
0 pF to 150 pF 20 165 ns
FS
X
or BCLK
X
, Whichever
Comes Later
t
SDB
Set-Up Time from D
R
Valid to 50 ns
BCLK
R/X
Low
t
HBD
Hold Time from BCLK
R/X
Low to 50 ns
D
R
Invalid
t
SF
Set-Up Time from FS
X/R
to Short Frame Sync Pulse (1 Bit Clock 50 ns
BCLK
X/R
Low Period Long)
t
HF
Hold Time from BCLK
X/R
Low Short Frame Sync Pulse (1 Bit Clock 100 ns
to FS
X/R
Low Period Long)
t
HBFI
Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns
Bit Clock Low to Frame Sync Clock Periods Long)
(FS
X
or FS
R
)
t
WFL
Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns
Sync Pulse (Low Level)
7