Datasheet

Connection Diagrams
Dual-In-Line Package
TL/H/5070–2
Top View
Plastic Chip Carrier
TL/H/5070–6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol Function
VPO
a
The non-inverted output of the receive power
amplifier.
GNDA Analog ground. All signals are referenced to
this pin.
VPO
b
The inverted output of the receive power
amplifier.
VPI Inverting input to the receive power amplifier.
VF
R
O Analog output of the receive filter.
V
CC
Positive power supply pin. V
CC
ea
5V
g
5%.
FS
R
Receive frame sync pulse which enables
BCLK
R
to shift PCM data into D
R
.FS
R
is an
8 kHz pulse train. See
Figures 2 and 3 for
timing details.
D
R
Receive data input. PCM data is shifted into
D
R
following the FS
R
leading edge.
BCLK
R
/ The bit clock which shifts data into D
R
after
the FS
R
leading edge. May vary from 64 kHz
CLKSEL
to 2.048 MHz. Alternatively, may be a logic
input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK
X
is used for both transmit and receive
directions (see Table I).
MCLK
R
/ Receive master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
PDN
asynchronous with MCLK
X
, but should be
synchronous with MCLK
X
for best
performance. When MCLK
R
is connected
continuously low, MCLK
X
is selected for all
internal timing. When MCLK
R
is connected
continuously high, the device is powered
down.
Symbol Function
MCLK
X
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R
. Best
performance is realized from synchronous
operation.
BCLK
X
The bit clock which shifts out the PCM data
on D
X
. May vary from 64 kHz to 2.048 MHz,
but must be synchronous with MCLK
X
.
D
X
The TRI-STATE
É
PCM data output which is
enabled by FS
X
.
FS
X
Transmit frame sync pulse input which
enables BCLK
X
to shift out the PCM data on
D
X
.FS
X
is an 8 kHz pulse train, see Figures 2
and 3 for timing details.
TS
X
Open drain output which pulses low during
the encoder time slot.
ANLB Analog Loopback control input. Must be set
to logic ‘0’ for normal operation. When pulled
to logic ‘1’, the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO
a
output of the receive power amplifier.
GS
X
Analog output of the transmit input amplifier.
Used to externally set gain.
VF
X
I
b
Inverting input of the transmit input amplifier.
VF
X
I
a
Non-inverting input of the transmit input
amplifier.
V
BB
Negative power supply pin. V
BB
eb
5V
g
5%.
2