Datasheet

Block Diagram
FIGURE 1 TL/H/5510– 2
Pin Description
Symbol Function
V
BB
Negative power supply pin.
V
BB
eb
5V
g
5%.
GNDA Analog ground. All signals are referenced
to this pin.
VF
R
O Analog output of the receive power ampli-
fier.
V
CC
Positive power supply pin.
V
CC
ea
5V
g
5%.
FS
R
Receive frame sync pulse which enables
BCLK
R
to shift PCM data into D
R
.FS
R
is
an 8 kHz pulse train. See
Figures 2 and 3
for timing details.
D
R
Receive data input. PCM data is shifted
into D
R
following the FS
R
leading edge.
BCLK
R
/CLKSEL The bit clock which shifts data into D
R
af-
ter the FS
R
leading edge. May vary from
64 kHz to 2.048 MHz. Alternatively, may
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK
X
is used for both transmit and re-
ceive directions (see Table I).
MCLK
R
/PDN Receive master clock. Must be
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLK
X
, but
Symbol Function
should be synchronous with MCLK
X
for best per-
formance. When MCLK
R
is connected continu-
ously low, MCLK
X
is selected for all internal tim-
ing. When MCLK
R
is connected continuously
high, the device is powered down.
MCLK
X
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
with MCLK
R
. Best performance is realized from
synchronous operation.
FS
X
Transmit frame sync pulse input which enables
BCLK
X
to shift out the PCM data on D
X
.FS
X
is
an 8 kHz pulse train, see
Figures 2 and 3 for
timing details.
BCLK
X
The bit clock which shifts out the PCM data on
D
X
. May vary from 64 kHz to 2.048 MHz, but
must be synchronous with MCLK
X
.
D
X
The TRI-STATE
É
PCM data output which is en-
abled by FS
X
.
TS
X
Open drain output which pulses low during the
encoder time slot.
GS
X
Analog output of the transmit input amplifier.
Used to externally set gain.
VF
X
I
b
Inverting input of the transmit input amplifier.
VF
X
I
a
Non-inverting input of the transmit input amplifi-
er.
2