Datasheet

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ZPLL
MibADC
64−Word
FIFO
HET
64 Words
HECC1
HECC2
SCI1
SCI2
I2C3
I2C2
I2C1
OSCIN
OSCOUT
PLLDIS
ADIN[11:0]
ADEVT
AD
REFHI
AD
REFLO
V
CCAD
V
SSAD
HET[0:8;18,20,22]
CAN1HTX
CAN1HRX
CAN2HTX
CAN2SRX
SCI1CLK
SCI1TX
SCI1RX
SCI2CLK
SCI2TX
SCI2RX
I2C3SDA
I2C3SCL
I2C2SDA
I2C2SCL
I2C1SDA
I2C1SCL
SCC
I2C4
I2C5
SCI3 SPI2 SPI1 ECP GIO/EBM
I2C4SDA
I2C4SCL
I2C5SDA
I2C5SCL
ICE Breaker
TMS470R1x CPU
TMS470R1x System Module
with Enhanced RTI Module
(A)
DMA Controller
16 Channels
Interrupt Expansion
Module (IEM)
Digital
Watchdog
(DWD)
Analog
Watchdog
(AWD)
Memory
Security
Module
(MSM)
FLASH
(1M Byte)
2 Banks
16 Sectors
RAM
(64K Bytes)
CPU Address Data Bus
Expansion Address/Data Bus
V
CCP
FLTP2
TRST
TCK
TDI
TDO
TMS
TMS2
RST
AWD
TEST
PORRST
CLKOUT
External
Pins Pins
External
Crystal
SCI3TX
SCI3RX
SCI3CLK
SPI2SCS
SPI2ENA
SPI2SIMO SPI2SOMI
SPI2CLK SPI1SCS
SPI1ENA
SPI1SIMO
GIOA[1]/INT[1]/ECLK
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOB[0]
GIOC[4:0] GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOF[7:0]
GIOG[7:0]
GIOH[5,0] SPI1SOMI
SPI1CLK
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
Functional Block Diagram
A. The enhanced RTI module is the system module with two extra bits to disable the ZPLL while in STANDBY mode.
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