Datasheet

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Parasitic
Capacitance
V
src
R
i
MibADC
Input Pin
R
s
Sample
Capacitor
C
i
R
leak
Sample Switch
External
     










     









 
  
 
 
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
Figure 22. MibADC Input Equivalent Circuit
Table 19. Multi-Buffer ADC Timing Requirements
MIN NOM MAX UNIT
t
c(ADCLK)
Cycle time, MibADC clock 0.05 µs
t
d(SH)
Delay time, sample and hold time 1 µs
t
d©)
Delay time, conversion time 0.55 µs
t
d(SHC)
(1)
Delay time, total sample/hold and conversion time 1.55 µs
(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
A. 1 LSB = (AD
REFHI
- AD
REFLO
)/2
10
Figure 23. Differential Nonlinearity (DNL)
54
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