Datasheet

www.ti.com

HIGH-END TIMER (HET) TIMINGS

Minimum PWM Output Pulse Width:

Minimum Input Pulses that Can Be Captured:

TMS470R1B1M

16/32-Bit RISC Flash Microcontroller

SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale

factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the

HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which

is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:

Once the input pulse width is greater than LRP, the resolution of the measurement is

still HRP. (That is, the captured value gives the number of HRP clocks inside the

pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr*lr/SYSCLK

Submit Documentation Feedback