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EXPANSION BUS MODULE TIMING
Expansion Bus Timing Parameters
CLKOUT
EBADDR
EBDATA
EBOE
EBCS0
EBHOLD
1 Hold State
Valid
Valid
t
c(CO)
t
d(COH-EBADV)
t
h(COH-EBADIV)
t
su(EBRDATV-COH)
t
h(COH-EBRDATIV)
t
d(COH-EBOE)
t
h(COH-EBOEH)
t
d(COH-EBCS0)
t
h(COH-EBCS0H)
t
su(COH-EBHOLDL)
t
su(COH-EBHOLDH)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
–40 ° C ≤ T
J
≤ 150 ° C, 3.0 V ≤ V
CC
≤ 3.6 V (see Figure 20 and Figure 21 )
MIN MAX UNIT
t
c(CO)
Cycle time, CLKOUT 20.8 ns
t
d(COH-EBADV)
Delay time, CLKOUT high to EBADDR valid 21.4 ns
t
h(COH-EBADIV)
Hold time, EBADDR invalid after CLKOUT high 12.4 ns
t
d(COH-EBOE)
Delay time, CLKOUT high to EBOE fall 11.4 ns
t
h(COH-EBOEH)
Hold time, EBOE rise after CLKOUT high 11.4 ns
t
d(COL-EBWR)
Delay time, CLKOUT low to write strobe ( EBWR) low 11.3 ns
t
h(COL-EBWRH)
Hold time, EBWR high after CLKOUT low 11.6 ns
t
su(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ)
(1)
15.2 ns
t
h(COH-EBRDATIV)
Hold time, EBDATA invalid after CLKOUT high (READ) (–14.7) ns
t
d(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid (WRITE)
(2)
16.1 ns
t
h(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE) 14.7 ns
SECONDARY TIMES
t
d(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall 13.6 ns
t
h(COH-EBCS0H)
Hold, EBCS0 rise after CLKOUT high 13.2 ns
t
su(COH-EBHOLDL)
Setup time, EBHOLD low to CLKOUT high
(1)
10.9 ns
t
su(COH-EBHOLDH)
Setup time, EBHOLD high to CLKOUT high
(1)
10.5 ns
(1) Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
(2) Valid after CLKOUT goes low for write cycles.
Figure 20. Expansion Memory Signal Timing - Reads
50
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