Datasheet

www.ti.com
I2C TIMING
I2C Signals (SDA and SCL) Switching Characteristics
(1)
t
w(SDAH)
t
r(SCL)
t
h(SDA−SCLL)
t
h(SCLL−SDAL)
t
w(SCLH)
t
f(SCL)
t
h(SCLL−SDAL
)
t
su(SCLH−SDAL)
t
w(SP)
t
su(SCLH−SDAH)
SDA
SCL
Stop Start Repeated Stop
t
c(SCL
)
t
w(SCLL)
t
su(SDA−SCLH)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
Table 11 assumes testing over recommended operating conditions.
STANDARD MODE FAST MODE
PARAMETER UNIT
MIN MAX MIN MAX
t
c(I2CCLK)
Cycle time, I2C module clock 75 150 75 150 ns
t
c(SCL)
Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated START
t
su(SCLH-SDAL)
4.7 0.6 µs
condition)
Hold time, SCL low after SDA low (for a repeated START
t
h(SCLL-SDAL)
4 0.6 µs
condition)
t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
t
su(SDA-SCLH)
Setup time, SDA valid before SCL high 250 100 ns
t
h(SDA-SCLL)
Hold time, SDA valid after SCL low For I2C bus devices 0 3.45
(2)
0 0.9 µs
t
w(SDAH)
Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
t
r(SCL)
Rise time, SCL 1000 20+0.1C
b
(3)
300 ns
t
r(SDA)
Rise time, SDA 1000 20+0.1C
b
(3)
300 ns
t
f(SCL)
Fall time, SCL 300 20+0.1C
b
(3)
300 ns
t
f(SDA)
Fall time, SDA 300 20+0.1C
b
(3)
300 ns
t
su(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs
t
w(SP)
Pulse duration, spike (must be suppressed) 0 50 ns
C
b
(3)
Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum t
h(SDA-SCLL)
for I2C bus devices needs to be met only if the device does not stretch the low period (t
w(SCLL)
) of the SCL
signal.
(3) C
b
= The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
A. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
B. The maximum t
h(SDA-SCLL)
needs only be met if the device does not stretch the LOW period (t
w(SCLL)
) of the SCL
signal.
C. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t
su(SDA-SCLH)
≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line t
r
max + t
su(SDA-SCLH)
.
D. C
b
= total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 19. I2C Timings
48
Submit Documentation Feedback