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SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode
(1) (2)
Data Valid
Data Valid
SCICLK
SCITX
SCIRX
t
c(SCC)
t
w(SCCH)
t
w(SCCL)
t
d(SCCHĆTXV)
t
v(TX)
t
su(RXĆSCCL)
t
v(SCCLĆRX)
TMS470R1B1M
16/32-Bit RISC Flash Microcontroller
SPNS109A – SEPTEMBER 2005 – REVISED AUGUST 2006
(see Figure 18 )
MIN MAX UNIT
t
c(SCC)
Cycle time, SCInCLK
(3)
8t
c(ICLK)
ns
t
w(SCCH)
Pulse duration, SCInCLK high 0.5t
c(SCC)
– 0.25t
c(ICLK)
0.5t
c(SCC)
+ 0.25t
c(ICLK)
ns
t
w(SCCL)
Pulse duration, SCInCLK low 0.5t
c(SCC)
– 0.25t
c(ICLK)
0.5t
c(SCC)
+ 0.25t
c(ICLK)
ns
t
d(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid 2t
c(ICLK)
+ 12 + t
r
ns
t
v(TX)
Valid time, SCInTX data after SCInCLK low 2t
c(SCC)
– 10 ns
t
su(RX-SCCL)
Setup time, SCInRX before SCInCLK low 0 ns
t
v(SCCL-RX)
Valid time, SCInRX data after SCInCLK low 2t
c(ICLK)
+ 10 ns
(1) t
c(ICLK)
= interface clock cycle time = 1/f
(ICLK)
(2) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(3) When driving an external SCInCLK, the following must be true: t
c(SCC)
≥ 8t
c(ICLK)
.
A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the
SCICLK falling edge.
Figure 18. SCIn Isosynchronous Mode Timing Diagram for External Clock
47
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